1. Field
Example embodiments relate to a counter and a phase locked loop (PLL), for example, to a counter capable of outputting a count value after holding the count value and a PLL having a counter capable of the same.
2. Description of the Related Art
Related art asynchronous counters, which may include a plurality of flip-flops, may count a clock signal by sequentially transmitting the clock signal through the flip-flops.
However, transmission delays are likely to occur in related art asynchronous counters during sequential transmission of a clock signal through the plurality of flip-flops. Due to such transmission delays, timing of the clock signal may vary from one flip-flop to another in a related-art asynchronous counter so that, for any time period, some flip-flops may have already received a clock signal and started counting the clock signal, whereas other flip-flops may have not even received the clock signal. Accordingly, a related art asynchronous counter may not be able to precisely count the clock signal. For example, if the flip-flops of the related art asynchronous counter have to output count values before completing clock signal transmission through the flip-flops, there is a high probability that the flip-flops will output inaccurate count values.
For example, in the case of counting a high-frequency clock signal, the time required for a clock signal to transmit through all flip-flops of a related art asynchronous counter is generally longer than the period of the clock signal, thus aggravating the aforementioned problem with related art asynchronous counters.
Phase locked loops (PLLs) are circuits that may output an oscillation clock signal with a desired locking frequency. PLLs may output an oscillation clock signal with a desired locking frequency by comparing the frequency of a current oscillation clock signal against a target locking frequency and accordingly altering the frequency of the current oscillation clock signal. In order to determine whether the frequency of a current oscillation clock signal is identical to a desired locking frequency, PLLs may learn the frequency of the current oscillation clock signal. However, since it may be impossible for related art asynchronous counters to accurately count a clock signal, PLLs may not precisely determine the frequency of a current oscillation clock signal and thus may not output an oscillation clock signal with a desired locking frequency.